1. Field
The present invention relates to semiconductor devices.
2. Description of the Related Art
Measures for electrically controlling the vehicle to increase the breakdown voltage of semiconductor chips or semiconductor packages used in various kinds of electronic control are needed more than ever today. For example, high anti-surge characteristics are required for an internal-combustion ignition device (hereinafter, referred to as an igniter) and resistance to a negative surge (hereinafter, referred to as a field decay surge), which is one of various kinds of surges, output from an inductive load needs to be improved.
For example, an IGBT (insulated gate bipolar transistor) has been known as the semiconductor device used in the igniter. FIG. 14 is a cross-sectional view illustrating the IGBT according to the related art. In the IGBT illustrated in FIG. 14, a p base region 102 and an n+ emitter region 103 are selectively provided in a surface layer of the front surface of an n− drift layer 101. A gate electrode 105 is provided on the front surface of the n− drift layer 101, with a gate insulating film 104 interposed therebetween. An emitter electrode 107 comes into contact with the p base region 102 and the n+ emitter region 103. In addition, the emitter electrode 107 is insulated from the gate electrode 105 by an interlayer insulating film 106.
An oxide film 108 covers the n− drift layer 101 exposed from the surface of the chip. An n+ buffer layer 109 and a p collector layer 110 are sequentially provided on a surface (rear surface) of the n− drift layer 101 which is opposite to the front surface in which the n+ emitter region 103 is provided. The impurity concentration of the n+ buffer layer 109 is about 5.4×1016 cm−3. The thickness t10 of the n+ buffer layer 109 is generally about 30 μm. A collector electrode 111 is provided on the surface of the p collector layer 110.
FIG. 15 is a cross-sectional view illustrating another example of the IGBT according to the related art. In the IGBT illustrated in FIG. 15, a breakdown voltage structure for ensuring a breakdown voltage is provided at the outer circumferential end of the chip. The breakdown voltage structure surrounds an active region in which a drift current flows. The active portion has the same structure as that in the IGBT illustrated in FIG. 14. In the breakdown voltage structure, a field limiting ring 112, which is a floating p+ region, is provided in a surface layer of an n− drift layer 101. In addition, an n+ stopper region 113 is provided in the surface layer of the n− drift layer 101 at the outer circumferential end of the chip.
A field plate electrode 114 comes into contact with the field limiting ring 112. A stopper electrode 115 comes into contact with an n+ stopper region 113. In addition, the stopper electrode 115 extends from the top of the n+ stopper region 113 to the surface of an oxide film 108. A p collector layer 110 is provided on the rear surface of the n− drift layer 101. The other structures are the same as those of the IGBT illustrated in FIG. 14.
As a semiconductor device having a current limit function for an overcurrent, a device has been proposed in which the distance between a sense IGBT and a main IGBT in the horizontal direction is equal to or more than 1500 μm and the amount of Hall current flowing (running) to the sense IGBT is reduced to prevent the oscillation of a current waveform during soft turn-off (for example, see the following Patent Document 1).
In addition, as a semiconductor device with improved surge resistance, a device has been proposed which includes: an insulated gate transistor that is formed in a chip and is arranged in a current path, with a high-voltage-side terminal or a low-voltage-side terminal connected to a load; a gate voltage boost element that is provided in the chip, with one end connected to a gate terminal of the insulated gate transistor, and is operated by a surge voltage applied from the high voltage side of the insulated gate transistor; a back-flow prevention element that is provided in the chip so as to be arranged in series between the gate terminal of the insulated gate transistor and the gate voltage boost element and prevents a back flow when a surge is applied; a clamping element that is provided between the low-voltage-side terminal and the gate terminal of the insulated gate transistor in the chip and clamps a voltage applied to the gate terminal of the insulated gate transistor to an operating voltage; a surge prevention element that is provided between the clamping element and the low-voltage-side terminal of the insulated gate transistor in the chip and prevents a surge from a ground line; a high-voltage-side connection pad that is formed in a peripheral portion of the chip and is connected to the high-voltage-side terminal of the insulated gate transistor; a boost element connection pad that is formed in the peripheral portion of the chip and is connected to one end of the gate voltage boost element; and a wiring material that is provided between a connection point provided outside the chip and the high-voltage-side connection pad connected to the high-voltage-side terminal of the insulated gate transistor, electrically connects the high-voltage-side connection pad to a boost element connection pad which is connected to the gate voltage boost element, is connected in parallel to the boost element connection pad, as viewed from the connection point, and serves as parasitic inductance when a surge is applied. In the device, the high-voltage-side connection pad connected to the high-voltage-side terminal of the insulated gate transistor and the boost element connection pad connected to the gate voltage boost element are not connected by wiring lines in the chip (for example, see the following Patent Document 2).